6th IEEE Symposium on Application Specific Processors

Sunday, June 8

9:00 Opening

9:15 Session 1: High Level Synthesis and Custom Instructions

Session chair: Elaheh Bozorgzadeh, University of California at Irvine, USA

Custom Processor Core Construction from C Code
Jelena Trajkovic and Daniel Gajski (University of California at Irvine, USA)

Resource Sharing in Custom Instruction Set Extensions
Marcela Zuluaga and Nigel Topham (University of Edinburgh, UK)

(S) Custom Instruction Generation with High-Level Synthesis
Kenshu Seto, Masahiro Fujita (Musashi Institute of Technology and University of Tokyo, Japan)

(S) Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor
Alexandros Papakonstantinou, Deming Chen, Wen-Mei Hwu (University of Illinois at Urbana-Champaign, USA)

10:55 Break

11:15 Keynote:

Application-Specific Processors for Client-side Computing: Opportunities and Pitfalls
Sanjay Patel, University of Illinois at Urbana-Champaign

12:15 Lunch

1:45 Session 2: Reconfigurable Computing

Session chair: Walid Najjar, University of California at Riverside, USA

Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi (University of Lugano, Switzerland)

Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures
Carlos Morra, João M. P. Cardoso, João Bispo, and Jürgen Becker (University of Karlsruhe, Germany, and INESC-ID, Portugal)

An FPGA Design Space Exploration Tool for Matrix Inversion Architectures
Ali Irturk, Bridget Benson, Shahnam Mirzae, Ryan Kastner (University of California at San Diego and University of California at Santa Barbara, USA)

3:15 Break

3:40 Session 3: Breakthrough Issues in Application Specific Processing

Session chair: Sami Yehia, Thales Group

Proving Functional Correctness of Weakly Programmable IPs - A Case Study with Formal Property Checking
Sacha Loitz, Markus Wedler, Christian Brehm, Timo Vogt, Norbert Wehn, and Wolfgang Kunz (University of Kaiserslautern, Germany)

Extensible On-Chip Peripherals
Bharat Sukhwani, Alessandro Forin, Richard Neil Pittman (Boston University and Microsoft Research, USA)

(S) Thermal-aware Design Considerations for Application-Specific Instruction Set Processor
Hai Lin, Guangyu Sun, Yunsi Fei, Yuan Xie, and Anand Sivasubramaniam (University of Connecticut and Pennsylvania State University, USA)

(S) Application Specific Low Latency Instruction Cache for NAND Flash Memory Based Embedded Systems
Kwangyoon Lee and Alex Orailoglu (University of California at San Diego, USA)

5:20p End of sessions

7:30p Social program: Ralph Brennan's Jazz Kitchen located in Disneyland downtown

Monday, June 9

9:00 Session 4: Multiprocessing

Session chair: Georgi Gaydadjiev, Delft University of Technology, The Netherlands

An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints
Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria (Politecnico di Milano, Italy)

AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications
Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato (Kyushu University, Japan)

(S) Energy and thermal tradeoffs in hardware-based load balancing for clustered multi-core architectures implementing power gating
Enric Musoll (ConSentry Networks, USA)

(S) System-Level Performance Estimation for Application-Specific MPSoC Interconnect Synthesis
Po-Kuan Huang, Matin Hashemi, Soheil Ghiasi (University of California at Davis, USA)

10:50 Break

11:15 Keynote

Anton, an Application-Specific Supercomputer for Molecular Dynamics Computations

Cliff Young, D. E. Shaw Research

12:15 Lunch

1:45 Panel

GP vs. ASP: Are ASIPS just a short-term transition in computing?
Moderator: Grant Martin, Tensilica
Panelists:
Eric Collins, Novelics
Tim Kogel, CoWare
Nigel Topham, University of Edinburgh and ARC
Nader Bagherzadeh, University of Irvine
Joerg Henkel, University of Karlsruhe

3:45 Break

4:10 Session 5: Applications

Session chair: Ryan Kastner, University of California at San Diego, USA

Accelerating Compute Intensive Applications with GPUs and FPGAs
Shuai Che, Jie Li, Jeremy W. Sheaffer, Kevin Skadron, John Lach (University of Virginia, USA)

TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing
Josef Spjut, Daniel Kopta, Spencer Kellis, Solomon Boulos, Erik Brunvand (University of Utah, USA)

(S) Multi-core Architectures with Dynamically Reconfigurable Array Processors for the WIMAX Physical Layer
Wei Han, Ying Yi, Mark Muir, Ioannis Nousias, Tughrul Arslan, Ahmet T. Edorgan (University of Edinburgh, UK)

(S) An MDCT Hardware Accelerator for MP3 Audio
Xingdong Dai and Meghanad D. Wagh (LSI Corporation and Lehigh University, USA)

5:50p End of Sessions

WASP, 2002

WASP, 2003

WASP, 2004

WASP, 2005

WASP, 2007